One of the most important things show at Intel’s 2018 Architecture day was not a CPU but a Phy. The reasons for this aren’t obvious so let SemiAccurate dig into the details.
The device shown was an Intel Falcon Mesa 10nm FPGA with 112Gbps SerDes, something that may not seem like a big deal. If you have any doubts that they are real you can take a look at the eye below, it is much cleaner than any eyes on the 112Gbps SerDes that the author has designed. (Note: Any eye would be better than ours since we have not ever designed one, this was meant as levity) There was also a demo showing that data could be sent and received across these transceivers, it wasn’t just pretty oscilloscope data.
Eye to eye to eye
So why is this important? For two reasons, the process and what wasn’t shown. The process is obviously 10nm which SemiAccurate has heard is a bit persnickety with anything even vaguely analog like, oh say, a SerDes. That said we are not trying to question this device, just pointing out what was the case. More importantly Intel did not show off 56Gbps SerDes even though they have them and are shipping them on Intel/Altera 14nm FPGAs. Here’s where things get a little funny as in the ‘ha ha’ sense, not the ‘political promises’ sense.
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Disclosures: Charlie Demerjian and Stone Arch Networking Services, Inc. have no consulting relationships, investment relationships, or hold any investment positions with any of the companies mentioned in this report.
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